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revision history as4c32m16sb-7tcn/as4c32m16sb-7tin/AS4C32M16SB-6TIN - 54pin tsopii package revision details date rev 1.0 preliminary datasheet jun 2016 alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc. reserves the right to change products or specification without notice AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 1/55 - rev.1.0 june 2016
features fast access time from clock: 5/5.4 ns fast clock rate: 166/143 mhz fully sync hronous operation internal pipelined architecture 8m word x 16-b it x 4-b ank programmable mode registers - cas latenc y : 2 or 3 - burst length: 1, 2, 4, 8, or full page - burst type: sequential or interleaved - burst s top function auto refresh and self refres h 8192 refres h c ycles/64ms cke power down mode single +3.3v 0.3v power supply operating t emperature range: - co mmercial: t a = 0~70c - industrial: t a = -40 ~85c interface: lvttl 54-p i n 400 mil plastic tsop ii pac k age - pb free and halogen free table 1. key specifications as4c32m16sb - 6/ 7 tck3 clock cycle time (min.) 6/7 tac3 access time from clk (max.) 5/5.4 tras row active time (min.) 42/42 trc row cycle time (min.) 60/63 table 2 . ordering information par t number frequency package temperature temp range as4c32m16sb - 7tcn 143mhz 54 pin tsop ii commercial 0c to 70 c as4c32m16sb - 7tin 143mhz 54 pin tsop ii industrial - 40c to 8 5c as4c32m16sb - 6tin 166mhz 54 pin tsop ii industrial - 40c to 8 5c th e 512mb sdram is a high -s peed cmos synchronous dram containing 512 mbits. it is internally configured as 4 banks of 8m word x 16 dram with a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). read and write ac cess es to the sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of a bank activate c ommand which is then followed by a read or wr ite c ommand. the sdram provides for programmable read or write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. an auto precharge function may be enabled to provide a self -t imed row precharge that is initiated at the end of the b urst sequence. the refresh functions, either auto or self refresh are easy to use. by having a programmable mode register, the system can choose the most suitable modes to maximize its performance. these devices are well suited for applications requiring h igh memory bandwidth and particularly well suited to high performance pc applications. overview AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 2/55 - rev.1.0 june 2016
figure 1. pin assignment (top view) 1 54 vdd vss 2 53 dq 0 dq 15 3 52 vddq vssq 4 51 dq 1 dq 14 5 50 dq 2 dq 13 6 49 vssq vddq 7 48 dq 3 dq 12 8 47 dq 4 dq 11 9 46 vddq vssq 10 45 dq 5 dq 10 11 44 dq 6 dq 9 12 43 vssq vddq 13 42 dq 7 dq 8 14 41 vdd vss 15 40 ldqm nc 16 39 we # udqm 17 38 cas # clk 18 37 ras # cke 19 36 cs # a 12 20 35 ba 0 a 11 21 34 ba 1 a9 22 33 a 10 / ap a8 23 32 a0 a7 24 31 a1 a6 25 30 a2 a5 26 29 a3 a4 27 28 vdd vss AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 3/55 - rev.1.0 june 2016
figure 2 . block diagram clk cke cs# ras# cas# we# clock buffer command decoder column counter control signal generator address buffer refresh counter buffer 8m x 16 cell array (bank #a) row decoder 8m x 16 cell array (bank #b) row decoder 8m x 16 cell array (bank #c) row decoder 8m x 16 cell array (bank #d) row decoder column decoder column decoder column decoder column decoder mode register dq15 dq0 ~ a10/ap a9 a11 a12 ba0 ba1 ~ a0 ldqm, udqm AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 4/55 - rev.1.0 june 2016
pin descriptions table 3 . pin details symbol type description clk input clock: clk is driven by the system clock. all sdram input signals are sampled on the positive edge of clk. clk also increments the internal burst counter and controls the output registers. cke input clock enable: cke activates (high) and deactivates (low) the clk signal. if cke goes low synchronously with clock (set - up and hold time same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the cke remains low. when all banks are in the idle state, deactivating the clock controls the entry to the power down and self refresh modes. cke is synchronous except after the device enters power down and self refresh modes, where cke becomes asynchronous until exiting the same mode. the input buffers, including clk, are disabled during power down and self refresh modes, providing low standby power. ba0,ba1 input bank activate : ba0, ba1 input select the bank for operation. ba1 ba0 select bank 0 0 bank #a 0 1 bank #b 1 0 bank #c 1 1 bank #d a0 - a1 2 input address inputs: a0 - a1 2 are sampled during the bankactivate command (row address a0 - a1 2 ) and read/write command (column address a0 - a 9 with a10 defining auto precharge) to select one location out of the 8 m available in the respective bank. during a precharge command, a10 is sampled to determine if all banks are to be precharged (a10 = high). the address inputs also provide the op - code during a mode register set command. cs# input chip select: cs# en ables (sampled low) and disables (sampled high) the command decoder. all commands are masked when cs# is sampled high. cs# provides for external bank selection on systems with multiple banks. it is considered part of the command code. ras# input row addre ss strobe: the ras# signal defines the operation commands in conjunction with the cas# and we# signals and is latched at the positive edges of clk. when ras# and cs# are asserted " low" and cas# is asserted "high " either the bankactivate command or the prec harge command is selected by the we# signal. when the we# is asserted "high " the bankactivate command is selected and the bank designated by b a is turned on to the active state . when the we# is asserted "low " the precharge command is selected and the bank designated by b a is switched to the idle state after the precharge operation. cas# input column address strobe: the cas# signal defines the operation commands in conjunction with the ras# and we# signals and is latched at the positive edges of clk. when r as# is held "high" and cs# is asserted "low" the column access is started by asserting cas# "low ". then, the read or write command is selected by asserting we# "low " or "high " . we# input write enable: the we# signal defines the operation commands in conju nction with the ras# and cas# signals and is latched at the positive edges of clk. the we# input is used to select the bankactivate or precharge command and read or write command. ldqm, udqm input data input/output mask: controls output buffers in read mo de and masks input data in write mode. AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 5/55 - rev.1.0 june 2016
dq0 - dq15 input / output data i/o: the dq0-1 5 input and output data are sy nchronized with the positive edges of clk. the i/os are maskabled during reads and writes. nc - no connect: these pins should be left unconne cted. v ddq suply dq power: provide isolated power to d qs for improved noise immunity. ( + 3.3v 0.3v ) v ssq supply dq ground: provide isolated ground to dqs for improved noise immunity. (0 v ) v dd supply power supply: + 3.3v 0.3v v ss supply ground AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 6/55 - rev.1.0 june 2016
operation mode fully synchronous operations are performed to latch the commands at the positive edges of clk . table 4 shows the truth table for the operation commands. tabl e 4 . truth table (note (1), (2) ) command state cke n - 1 cke n dqm ba 0,1 a 10 a 0- 9,11 -12 cs# ras# cas# we# bankactivate idle (3) h x x v row address l l h h bankprecharge any h x x v l x l l h l prechargeall any h x x x h x l l h l write active (3) h x v v l column address (a0 ~ a 9) l h l l write and autopre charge active (3) h x v v h l h l l read active (3) h x v v l column address (a0 ~ a 9 ) l h l h read and autoprecharge active (3) h x v v h l h l h mode register set idle h x x op code l l l l no - operation any h x x x x x l h h h burst stop active (4) h x x x x x l h h l device deselect any h x x x x x h x x x autorefresh idle h h x x x x l l l h selfrefresh entry idle h l x x x x l l l h selfrefresh exit idle l h x x x x h x x x (selfrefresh) l h h h clock suspend mode entry active h l x x x x h x x x l v v v power down mode entry any (5) h l x x x x h x x x l h h h clock suspend mode exit active l h x x x x x x x x power down mode exit any l h x x x x h x x x (powerdown) l h h h data write/output enable active h x l x x x x x x x data mask/output disable active h x h x x x x x x x note: 1. v= valid , x =don't care , l =low level , h=high level 2. cke n signal is input level when commands are provided. cke n - 1 signal is input level one clock cycle before the commands ar e provided. 3. these are states of bank designated by b a signal. 4. device state is 1, 2, 4, 8, and full page burst operation. 5. power down mode can not enter in the burst operation. when this command is asserted in the burst cycle, device state is cloc k suspend mode. AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 7/55 - rev.1.0 june 2016
commands 1 bankactivate (ras# = "l", cas# = "h", we# = "h", bas = bank, a0 - a1 2 = row address) the bankactivate command activates the idle bank designated by the ba0 , 1 signals . by latching the row address on a0 to a1 2 at the time of this command, the selected row access is initiated. the read or write operation in the same bank can occur after a time delay of t rcd (min.) from the time of bank activation. a subsequent bankactivate command to a different row in the same bank can only be issued after the previous active row has been precharged (refer to the following figure). the minimum time interval between successive bankactivate commands to the same bank is defined by t rc (min.). the sdram has four internal banks on the same chip and sh ares part of the internal circuitry to reduce chip area; therefore it restricts the back - to - back activation of the two banks. t rrd (min.) specifies the minimum time required between activating different banks. after this command is used, the write command a nd the block write command perform the no mask write operation. clk command t0 t1 address t2 t3 tn+3 tn+4 tn+5 tn+6 ras# - cas# delay(t rcd ) ras# - ras# delay time(t rrd ) ras# - cycle time(t rc ) autoprecharge begin bank a row addr. bank a col addr. bank b row addr. bank a row addr. bank a activate nop nop r/w a with autoprecharge bank b activate nop nop bank a activate dont care figure 3 . bankactivate command cycle (burst length = n) 2 bankprecharge command (ras# = "l", cas# = "h", we# = "l", bas = bank, a10 = "l", a0 - a9 , a11 and a 12 = don't care) the bankprecharge command precharges the bank disignated by ba signal. the precharged bank is switched from the active state to the idle state. this command can be asserted anytime after t ras (min.) is satisfied from the bankactivate com mand in the desired bank. the maximum time any bank can be active is specified by t ras (max.). therefore, the precharge function must be performed in any active bank within t ras (max.). at the end of precharge, the precharged bank is still in the idle state and is ready to be activated again. 3 prechargeall command (ras# = "l", cas# = "h", we# = "l", bas = dont care, a10 = "h", a0 - a9 , a11 and a12 = don't care) the prechargeall command precharges all banks simultaneously and can be issued even if all ba nks are not in the active state. all banks are then switched to the idle state. 4 read command (ras# = "h", cas# = "l", we# = "h", bas = bank, a10 = "l", a0 - a 9 = column address) the read command is used to read a burst of data on consecutive clock cy cles from an active row in an active bank. the bank must be active for at least t rcd (min.) before the read command is issued. during read bursts, the valid data - out element from the starting column address will be available following the cas latency after the issue of the read command. each subsequent data - out element will be valid by the next positive clock edge (refer to the following figure). the dqs go into high - impedance at the end of the burst unless other command is initiated. the burst length, burst sequence, and cas latency are determined by the mode register, which is already programmed. a full - page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 8/55 - rev.1.0 june 2016
clk command t0 t1 t2 t3 t4 t5 t6 read a nop nop nop nop nop nop nop t7 t8 nop cas# latency=2 t ck2 , dq cas# latency=3 t ck3 , dq dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 figure 4. burst read operation ( burst length = 4, cas# latency = 2, 3) the read data appears on the dqs subject to the values on the dqm inputs two clocks earlier (i.e. dqm latency is two clocks for output buffers). a read burst without the auto precharge function may be interrupted by a subsequent read or write command to the same bank or the other active bank before the end of the burst length. it may be interrupted by a bankprecharge/ prechargeall command to the same bank too. the interrupt coming from the read comm and can occur on any clock cycle following a previous read command (refer to the following figure). clk command t0 t1 t2 t3 t4 t5 t6 read a read b nop nop nop nop nop nop t7 t8 nop cas# latency=2 t ck2 , dq cas# latency=3 t ck3 , dq dout a 0 dout b 0 dout b 1 dout b 2 dout a 0 dout b 0 dout b 1 dout b 2 dout b 3 dout b 3 figure 5. read interrupted by a read (burst length = 4, cas# latency = 2, 3) the dqm inputs are used to avoid i/o cont ention on the dq pins when the interrupt comes from a write command. the dqms must be asserted (high) at least two clocks prior to the write command to suppress data - out on the dq pins. to guarantee the dq pins against i/o contention, a single cycle with h igh - impedance on the dq pins must occur between the last read data and the write command (refer to the following three figures). if the data output of the burst read occurs at the second clock of the burst write, the dqms must be asserted (high) at least o ne clock prior to the write command to avoid internal bus contention. clk command t0 t1 t2 t3 t4 t5 t6 nop nop bank a activate nop nop read a write a nop t7 t8 nop cas# latency=2 t ck2 , dq dqm t9 nop din a 0 din a 1 din a 2 din a 3 figure 6. read to write interval (burst length 4, cas# latency = 2) AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 9/55 - rev.1.0 june 2016
clk command t0 t1 t2 t3 t4 t5 t6 nop nop read a nop nop write b nop nop t7 t8 nop dqm din b 0 din b 1 din b 2 din b 3 cas# latency=2 t ck2 , dq must be hi-z before the write command dont care figure 7. read to write interval (burst length 4, cas# latency = 2) clk command t0 t1 t2 t3 t4 t5 t6 nop read a nop nop nop nop write b nop t7 t8 nop dqm dout a 0 din b 0 din b 1 din b 2 cas# latency=3 t ck3 , dq must be hi-z before the write command dont care figure 8. read to write interval (burst length R 4, cas# latency = 3) a read burst without the auto precharge function may be interrupted b y a bankprecharge/ prechargeall command to the same bank. the following figure shows the optimum time that bank precharge/ prechargeall command is issued in different cas latency. clk command t0 t1 t2 t3 t4 t5 t6 read a nop nop nop precharge nop nop activate t7 t8 nop cas# latency=2 t ck2 , dq cas# latency=3 t ck3 , dq dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 address bank, col a bank (s) bank row t rp figure 9. read to precharge (cas# latency = 2, 3) AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 10/55 - rev.1.0 june 2016
5 read and autoprecharge command (ras# = "h", cas# = "l", we# = "h", bas = bank, a10 = "h", a0 - a 9 = column address) the read and autoprecharge command automatically performs the precharge operation after the read operation. once this comma nd is given, any subsequent command cannot occur within a time delay of { t rp (min.) + burst length } . at full - page burst, only the read operation is performed in this command and the auto precharge function is ignored. 6 write command (ras# = "h", cas# = "l", we# = "l", bas = bank, a10 = "l", a0 - a 9 = column address) the write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank. the bank must be active for at least t rcd (min.) before the write command is issued. during write bursts, the first valid data - in element will be registered coincident with the write command. subsequent data elements will be registered on each successive positive clock edge (refer to the following figure). the dqs remain with h igh - impedance at the end of the burst unless another command is initiated. the burst length and burst sequence are determined by the mode register, which is already programmed. a full - page burst will continue until terminated (at the end of the page it wil l wrap to column 0 and continue). clk dq t0 t1 t2 t3 t4 t5 t6 din a 0 din a 1 din a 2 din a 3 dont care t7 t8 command nop write a nop nop nop nop nop nop nop the first data element and the write are registered on the same clock edge figure 1 0 . burst write operation (burst length = 4) a write burst without the auto precharge function may be interrupted by a subsequent write, bankprecharge/prechargeall, or read com mand before the end of the burst length. an interrupt coming from write command can occur on any clock cycle following the previous write command (refer to the following figure). clk dq t0 t1 t2 t3 t4 t5 t6 din a 0 din b 0 din b 1 din b 2 din b 3 t7 t8 command nop write a write b nop nop nop nop nop nop figure 1 1 . write interrupted by a write (burst length = 4) the read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock edge in which the last data - in element is registered. in order to avoid data contention, input data must be rem oved from the dqs at least one clock cycle before the first read data appears on the outputs (refer to the following figure). once the read command is registered, the data inputs will be ignored and writes will not be executed. AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 11/55 - rev.1.0 june 2016
clk command t0 t1 t2 t3 t4 t5 t6 nop write a read b nop nop nop nop nop t7 t8 nop cas# latency=2 t ck2 , dq cas# latency=3 t ck3 , dq dout b 0 dout b 1 dout b 2 dout b 3 dout b 0 dout b 1 dout b 2 dout b 3 din a 0 dont care din a 0 dont care dont care input data must be removed from the dq at least one clock cycle before the read data appears on the outputs to avoid data contention figure 12. write interrupted by a read (burst length = 4, cas# latency = 2, 3) the bankprecharge/prechargeall command that interrupts a write burst without the auto precharge function should be issued m cycles after the clock edge in which the last data - in element is registered, where m equals t wr /t ck rounded up to the next whole number. in addition, the dqm signals must be used to mask input data, starting with the clock edge following the last data - in element and ending with the clock edge on which the bankprecharge/prechargeall command is entered (refer to the following figure). clk command t0 t1 t2 t3 t4 t5 t6 write nop nop precharge nop nop activate nop t7 dqm dont care address bank col n bank (s) row t rp din n din n+1 t wr dq note: the dqms can remain low in this example if the length of the write burst is 1 or 2. figure 13. write to precharge 7 wr ite and autoprecharge command (ras# = "h", cas# = "l", we# = "l", bas = bank, a10 = "h", a0 -a9 = column address) the write and autoprecharge command performs the precharge operation automatically after the write operation. once this command is given, a ny subsequent command can not occur within a time delay of { (burst length - 1) + t wr + t rp (min.) } . at full - page burst, only the write operation is performed in this command and the auto precharge function is ignored. AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 12/55 - rev.1.0 june 2016
clk dq t0 t1 t2 t3 t4 t5 t6 din a 0 din a 1 t7 t8 command bank a activate nop nop write a auto precharge nop nop nop nop nop t9 bank a activate t dal =t wr +t rp t dal begin autoprecharge bank can be reactivated at completion of t dal figure 14. burst write with auto-precharge (burst length = 2) 8 mode register set command (ras# = "l", cas# = "l", we# = "l", a0 - a1 2 = register data) the mode register stores the data for controlling the various operating modes of sdram. the mode register se t command programs the values of cas latency, addressing mode and burst length in the mode register to make sdram useful for a variety of different applications. the default values of the mode register after power - up are undefined; therefore this command must be issued at the power - up sequence. the state of pins a0~ a1 2 in the same cycle is the data written to the mode register. two clock cycle s are required to complete the write in the mode register (refer to the following figure). the contents of the mode register can be changed using the same command and the clock cycle requirements during operation as long as all banks are in the idle state. table 5. mode register bitmap ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 rfu* 0 rfu* wbl te s t m o d e cas lat ency bt burst lengt h a9 write burst length a8 a7 te s t m o d e a3 burst type 0 burst 0 0 normal 0 sequential 1 single bit 1 0 vendor use only 1 interleave 0 1 vendor use only a6 a5 a4 cas latency a2 a1 a0 burst length 0 0 0 reserved 0 0 0 1 0 0 1 reserved 0 0 1 2 0 1 0 2 clocks 0 1 0 4 0 1 1 3 clocks 0 1 1 8 1 0 0 reserved 1 1 1 full page (sequential ) all other reserved all other reserved *note: rfu (reserved for future use) should stay 0 during mrs cycle. AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 13/55 - rev.1.0 june 2016
clk cs# t0 t1 t2 t3 t4 t5 t6 t7 cke dont care ras# t mrd cas# t8 t9 t10 we# ba0,1 a10 a0-a9, a11-a12 dqm dq t rp prechargeall mode register set command any command hi-z address key figure 1 5 . mode register set cycle burst length field (a2~a0) this field specifies the data length of column access using the a2~a0 pins and selects the burst leng th to be 2, 4, 8, or full page. table 6. burst length field a2 a1 a0 burst length 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 full page full page length: 512 AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 14/55 - rev.1.0 june 2016
burst type fie ld (a3) the addressing mode can be one of two modes, interleave mode or sequential mode. sequential mode supports burst length of 1, 2, 4, 8, or full page, but interleave mode only supports burst length of 4 and 8. table 7. addressing mode select field a3 burst type 0 sequential 1 interleave burst definition, addressing sequence of sequential and interleave mode table 8. burst definition burst length start address sequential interleave a2 a1 a0 2 x x 0 0, 1 0, 1 x x 1 1, 0 1, 0 4 x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 x 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2 , 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 full page location = 0 - 511 n, n+1, n+2, n+3, 511 , 0, 1, 2, n - 1, n, not support cas latency field (a6~a4) this field specifies the number of clock cycles from the assertion of the read command to the firs t read data. the minimum whole value of cas latency depends on the frequency of clk. the minimum whole value satisfying the following formula must be programmed into this field. t cac (min) cas latency x t ck table 9. cas latency a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 clocks 0 1 1 3 clocks 1 x x reserved AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 15/55 - rev.1.0 june 2016
test mode field (a8~a7) these two bits are used to enter the test mode and must be programmed to "00" in normal operation. table 10. test mode a8 a7 test mode 0 0 normal mode 0 1 vendor use only 1 x vendor use only write burst length (a9) this bit is used to select the write burst l ength . when the a9 bit is "0", the burst - read - burst - write mode is selected. when the a9 bit is "1", the burst - read - single - write mode is selected. table 11. write burst length a9 write burst length 0 burst - read - burst - write 1 burst - read - single - write note: a10 and ba0 , 1 should st ay l during mode set cycle. 9 no - operation command (ras# = "h", cas# = "h", we# = "h") the no - operation command is used to perform a nop to the sdram which is selected (cs# is low). this prevents unwanted commands from being registered during idle o r wait states. 10 burst stop command (ras# = "h", cas# = "h", we# = "l") the burst stop command is used to terminate either fixed - length or full - page bursts. this command is only effective in a read/write burst without the auto precharge function. t he terminated read burst ends after a delay equal to the cas latency (refer to the following figure). the termination of a write burst is shown in the following figure. clk command t0 t1 t2 t3 t4 t5 t6 read a nop nop nop burst stop nop nop nop t7 t8 nop cas# latency=2 t ck2 , dq cas# latency=3 t ck3 , dq dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 the burst ends after a delay equal to the cas# latency figure 1 6 . termination of a burst read operation (burst length 4, cas# latency = 2, 3) AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 16/55 - rev.1.0 june 2016
clk dq t0 t1 t2 t3 t4 t5 t6 din a 0 din a 1 din a 2 dont care t7 t8 command nop write a nop nop burst stop nop nop nop nop figure 1 7 . termination of a burst write operation (burst length = x) 11 device deselect command (cs# = "h") the device deselect command disables the command decoder so that the ras#, cas#, we# and address inputs are ignored, regardless of whether the clk is enabled. this command is similar to the no operation command. 12 autorefresh command (ras# = "l", cas# = "l", we# = "h" , cke = "h", a0 - a 12 = don't care) the autorefresh command is used du ring normal operation of the sdram and is analogous to cas# - before - ras# (cbr) refresh in conventional drams. this command is non - persistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controlle r. this makes the address bits a "don't care" during an autorefresh command. the internal refresh counter increments automatically on every auto refresh cycle to all of the rows. the refresh operation must be performed 819 2 times within 64 ms. the time requ ired to complete the auto refresh operation is specified by t rc (min.). to provide the autorefresh command, all banks need to be in the idle state and the device must not be in power down mode (cke is high in the previous cycle). this command must be follow ed by nops until the auto refresh operation is completed. the precharge time requirement, t rp (min), must be met before successive auto refresh operations are performed. 13 selfrefresh entry command (ras# = "l", cas# = "l", we# = "h", cke = "l", a0 - a 12 = don't care) the selfrefresh is another refresh mode available in the sdram. it is the preferred refresh mode for data retention and low power operation. once the selfrefresh command is registered, all the inputs to the sdram become "don't care" with t he exception of cke, which must remain low. the refresh addressing and timing is internally generated to reduce power consumption. the sdram may remain in selfrefresh mode for an indefinite period. the selfrefresh mode is exited by restarting the external clock and then asserting high on cke (selfrefresh exit command). 14 selfrefresh exit command this command is used to exit from the selfrefresh mode. once this command is registered, nop or device deselect commands must be issued for t xsr (min.) because time is required for the completion of any bank currently being internally refreshed. if auto refresh cycles in bursts are performed during normal operation, a burst of 819 2 auto refresh cycles should be completed just prior to entering and just after exit ing the selfrefresh mode. 15 clock suspend mode entry / powerdown mode entry command (cke = "l") when the sdram is operating the burst cycle, the internal clk is suspended (masked) from the subsequent cycle by issuing this command (asserting cke "low") . the device operation is held intact while clk is suspended. on the other hand, when all banks are in the idle state, this command performs entry into the powerdown mode. all input and output buffers (except the cke buffer) are turned off in the powerdown mode. the device may not remain in the clock suspend or powerdown state longer than the refresh period (64ms) since the command does not perform any refresh operations. AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 17/55 - rev.1.0 june 2016
16 clock suspend mode exit / powerdown mode exit command (cke= "h") when the int ernal clk has been suspended, the operation of the internal clk is reinitiated from the subsequent cycle by providing this command (asserting cke "high" , the command should be nop or deselect ). when the device is in the powerdown mode, the device exits thi s mode and all disabled buffers are turned on to the active state. t pde (min.) is required when the device exits from the powerdown mode. any subsequent commands can be issued after one clock cycle from the end of this command. 17 data write / output enab le, data mask / output disable command (dqm = "l", "h") during a write cycle, the dqm signal functions as a data mask and can control every word of the input data. during a read cycle, the dqm functions as the controller of output buffers. dqm is also u sed for device selection, byte selection and bus control in a memory system. AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 18/55 - rev.1.0 june 2016
table 12. absolute maximum rating symbol item values unit note v in , v out input, output voltage - 1.0 ~ 4.6 v 1 v dd , v ddq power supply voltage - 1.0 ~ 4.6 v 1 t a ambient temp erature commercial 0 ~ 70 c 1 industrial - 4 0 ~ 85 c 1 t stg storage temperature -5 5 ~ 150 c 1 t solder soldering temperature (10 second s) 260 c 1 p d power dissipation 1 w 1 i os short circuit output current 50 ma 1 table 13. recommended d.c. oper ating conditions (v dd = 3.3v 0.3v, t a = - 4 0~ 85 c) symbol parameter min. typ. max. unit note v dd power supply voltage 3.0 3. 3 3.6 v 2 v ddq power supply voltage(for i/o buffer) 3.0 3.3 3.6 v 2 v ih lvttl input high voltage 2.0 - v ddq +0.3 v 2 v il lvttl input low voltage - 0.3 - 0.8 v 2 i il input leakage current ( 0v vin vdd, all other pins not under test = 0v ) - 10 - 10 a i o z output leakage current output disable, 0v v out v ddq ) - 10 - 10 a v oh lvttl output "h" level voltage ( i out = - 2ma ) 2 .4 - - v v ol lvttl output "l" level voltage ( i out = 2ma ) - - 0.4 v table 14. capacitance (v dd = 3.3v, t a = 25 c) symbol parameter min. max. unit c i input capacitance 3.5 5.5 pf c i/o input/output capacitance 4 6 pf note: these parameters are perio dically sampled and are not 100% tested. AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 19/55 - rev.1.0 june 2016
table 15. d.c. characteristics (v dd = 3.3v 0.3v, t a = - 4 0~ 85 c) description/test condition symbol - 6 -7 unit note max. operating current t rc t rc (min), outputs open , one bank active i dd1 120 110 ma 3 p recharge standby current in non - power down mode t ck = 15ns , cs# v ih (min), cke v ih input signals are changed every 2clks i dd2n 50 40 precharge standby current in non - power down mode t ck = , clk v il (max), cke v ih i dd2ns 36 36 precharge standby current in power down mode t ck = 15ns , cke v il (max) i dd2p 4 4 precharge standby current in power down mode t ck = , cke v il (max) i dd2ps 4 4 active standby current in non - power down mode t ck = 15ns , cke v ih (min), cs# v ih (min) input signals ar e changed every 2clks i dd3n 70 60 active standby current in non - power down mode cke v ih (min), clk v il (max), t ck = i dd3ns 70 60 operating current (burst mode) t ck =t ck (min), outputs open, multi - bank interleave i dd4 124 120 3, 4 refresh current t rc t rc (min) i dd5 160 150 3 self refresh current cke 0.2v ; for other inputs v ih R v dd - 0.2v, v il 0.2v i dd6 4 4 AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 20/55 - rev.1.0 june 2016
table 16. electrical characteristics and recommended a.c. operating conditions (v dd = 3.3v 0.3v, t a = - 4 0~ 85 c) (note: 5, 6, 7, 8) symbol a.c. parameter - 6 -7 unit note min. max. min. max. t rc row cycle time ( same bank) 60 - 63 - ns t rfc refresh cycle time 60 - 63 - t rcd ras# to cas# delay (same bank) 18 - 21 - t rp precharge to refresh/row activate command (same bank) 18 - 21 - t rrd row activate to row activate delay (different banks) 12 - 14 - t m rd mode register set cycle time 12 - 14 - t ras row activate to precharge time (same bank) 42 120 k 42 120 k t wr write recovery time 12 - 14 - t ck clock cycle time cl* = 2 10 - 10 - 9 cl* = 3 6 - 7 - t ch clock high time 2 - 2.5 - 10 t cl cloc k low time 2 - 2. 5 - 10 t ac access time from clk (positive edge) cl* = 2 - 6 - 6 10 cl* = 3 - 5 - 5.4 t oh data output hold time 2.5 - 2.5 - 9 t lz data output low impedance 0 - 0 - t hz data output high impedance - 5 - 5.4 8 t is data/address/control input set - up time 1. 5 - 1. 5 - 10 t ih data/address/control input hold time 0.8 - 0.8 - 10 t pde power down exit set - up time t is+ t ck - t is+ t ck - t r efi average refresh interval time - 7.8 - 7.8 s t xsr exit self - refresh to any command t rc+ t is - t rc+ t is - ns * cl is cas latency. note: 1. stress greater than those listed under "absolute maximum ratings" may cause permanent damage to t he device. absolute maximum dc requirements contain stress ratings only. functional operation at the absolute maximum limits is not implied or guaranteed. extended exposure to maximum ratings may affect device reliability. 2. all voltages are referenced to v ss . overshoot v ih (max) = 4.6v for pulse width 3 ns. und ershoot v il (min) = - 1.0v for pulse width 3 ns. 3. these parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of t ck and t rc . input signals are changed one time during every 2 t ck . 4. these parameters depend on the output loading. specified values are obtained with the output open. 5. power - up sequence is described in note 11. 6. a.c. test conditions AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 21/55 - rev.1.0 june 2016
table 17. lvttl interface reference level of output signals 1.4v / 1.4v output load reference to the under output load (b) input signal levels 2.4v / 0.4v transition time (rise and fall) of input signals 1ns reference level of input signals 1.4v output 1.2k 30pf 3.3v 870 output z0=50 50 30pf 1.4v figure 1 8 .1 lvttl d.c. test load (a) figure 1 8 .2 lvttl a.c. test load (b) 7. transition times are measured between v ih and v il . transition ( rise and fall) of input signals are in a fixed slope (1 ns). 8. t hz defines the time in which the outputs achieve the open circuit condition a nd are not at reference levels. 9. if clock ris ing time is longer than 1 ns, ( t r / 2 - 0.5) ns should be added to the parameter. 10. assumed input rise and fall time t t ( t r & t f ) = 1 ns if t r or t f is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns should be added to the parameter. 11. power up sequence power up must be performed in the following sequence. 1) power must be applied to v dd and v ddq ( simultaneously) when cke = low , dqm = high and all input sig nals are held "nop" state. 2) start clock and maintain stable condition for minimum 200 s, then bring cke high and , it is recommended that dqm is held "high" (v dd levels) to ensure dq output is in high impedance. 3) all banks must be precharged. 4) mode register set command must be asserted to initialize the mode register. 5) a minimum of 2 auto - refresh dummy cycles must be required to stabilize the internal circuitry of the device. * the auto refresh command can be issue before or after mode register set command AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 22/55 - rev.1.0 june 2016
timing waveforms figure 19 . ac parameters for write timing (burst length =4) t0 t1 t2 dont care t ch activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t cl begin auto precharge bank b rax rbx ray rax cax rbx cbx ray cay ax0 ax1 ax2 ax3 bx0 bx1 bx2 bx3 ay0 ay1 ay2 ay3 t rcd t rc t dal t wr write with auto precharge command bank a activate command bank b write with auto precharge command bank b activate command bank a write command bank a precharge command bank a t is t is t ih t ih t is begin auto precharge bank a t is t ih hi-z clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11-a12 dqm dq AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 23/55 - rev.1.0 june 2016
figure 2 0 . ac parameters for read timing (burst length=2, cas# latency=2) hi-z clk cs# t0 t1 t2 cke dont care ras# t ch cas# we# ba0,1 a10 a0-a9, a11-a12 dqm dq activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t cl begin auto precharge bank b rax rbx rax cax rbx cbx ray ray ax0 ax1 t rrd t rc read command bank a activate command bank b read with auto precharge command bank b activate command bank a t is t ih t ih t is t is t ih t ras t rcd t ac t lz t hz bx0 bx1 t hz t rp precharge command bank a t oh AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 24/55 - rev.1.0 june 2016
figure 2 1 . auto refresh (burst length=4, cas# latency=2) t0 t1 t2 dont care precharge all command t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 rax cax rax ax0 ax1 t rp t rc auto refresh command auto refresh command activate command bank a read command bank a t rc t rcd clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11-a12 dqm dq AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 25/55 - rev.1.0 june 2016
figure 2 2 . power on se quen c e and auto refresh hi-z t0 t1 t2 dont care inputs must be stable for 200s t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t mrd mode register set command high level is reguired minimum for 2 refresh cycles are required t rp precharge all command 1st auto refresh (*) command 2nd auto refresh (*) command any command note (*) : the auto refresh command can be issue before or after mode register set command clk cs# cke ras# cas# we# ba0,1 a10 a0-a9 a11-a12 dqm dq address key AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 26/55 - rev.1.0 june 2016
figure 2 3 . self refresh entry & exit cycle t0 t1 t2 dont care self refresh entry t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 self refresh exit auto refresh t is hi-z t is t ih *note 1 *note 2 *note 3,4 t pde *note 5 *note 6 *note 7 t xsr *note 8 hi-z *note 9 clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11-a12 dqm dq note: to enter selfrefresh mode 1. cs#, ras# & cas# with cke should be low at the same clock cycle. 2. after 1 clock cycle, all th e inputs including the system clock can be don't care except for cke. 3. the device remains in selfrefresh mode as long as cke stays "low". 4. once the device enters selfrefresh mode, minimum t ras is required before exit from selfrefresh. to exit selfrefresh mod e 5. system clock restart and be stable before returning cke high. 6. enable cke and cke should be set high for valid setup time and hold time . 7. cs# starts from high. 8. minimum t xsr is required after cke going high to complete selfrefresh exit. 9. 8192 cycles of burst autorefresh is required before selfrefresh entry and after selfrefresh exit if the system uses burst refresh. AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 27/55 - rev.1.0 june 2016
figure 2 4 . 1 . clock suspension during burst read (using cke) (burst length=4, cas# latency=2) hi-z t0 t1 t2 dont care t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 rax rax cax activate command bank a read command bank a ax0 ax1 ax2 ax3 t hz clock suspend 1 cycle clock suspend 2 cycles clock suspend 3 cycles clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11-a12 dqm dq AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 28/55 - rev.1.0 june 2016
figure 2 4 . 2 . clock suspension during burst read (using cke) (burst length=4, cas# latency=3) hi-z t0 t1 t2 dont care t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 rax rax cax activate command bank a read command bank a ax0 ax1 ax2 ax3 t hz clock suspend 1 cycle clock suspend 2 cycles clock suspend 3 cycles clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11-a12 dqm dq AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 29/55 - rev.1.0 june 2016
figure 2 5 . clock suspension during burst write (using cke) (burst length=4) hi-z t0 t1 t2 dont care t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 rax rax cax activate command bank a write command bank a clock suspend 1 cycle clock suspend 2 cycles clock suspend 3 cycles dax0 dax1 dax2 dax3 clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11-a12 dqm dq AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 30/55 - rev.1.0 june 2016
figure 2 6 . power down mode and clock suspension (burst leng th =4, cas# latency=2) hi-z t0 t1 t2 dont care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t is power down mode exit t pde power down mode entry read command bank a clock suspension start power down mode exit t ih rax rax cax ax0 ax1 ax3 ax2 active standby clock suspension end precharge command bank a power down mode entry precharge standby any command valid t hz clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11-a12 dqm dq AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 31/55 - rev.1.0 june 2016
figure 2 7 . 1 . random column read (page within same bank) (burst length=4, cas# late ncy=2) hi-z t0 t1 t2 dont care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a raw raw cax aw0 aw1 ay2 precharge command bank a raz caw cay raz caz aw2 aw3 ax0 ax1 ay0 ay1 ay3 az0 read command bank a read command bank a activate command bank a read command bank a clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11-a12 dqm dq AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 32/55 - rev.1.0 june 2016
figure 2 7 . 2 . random column read (page within same bank) (burst length=4, cas# latency=3) hi-z t0 t1 t2 dont care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a raw raw cax aw0 aw1 ay2 precharge command bank a raz caw cay raz caz aw2 aw3 ax0 ax1 ay0 ay1 ay3 read command bank a read command bank a activate command bank a read command bank a clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11-a12 dqm dq AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 33/55 - rev.1.0 june 2016
figure 2 8 . random column write (page within same bank) (burst length=4) hi-z t0 t1 t2 dont care activate command bank b t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 write command bank b rbw rbw cbx dbw0 dbw1 dby2 precharge command bank b clk rbz cbw cby rbz cbz dbw2 dbw3 dbx0 dbx1 dby0 dby1 dby3 write command bank b write command bank b activate command bank b write command bank b cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11-a12 dqm dq dbz0 dbz1 AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 34/55 - rev.1.0 june 2016
figure 29 . 1 . random row read (interleaving banks) (burst length=8, cas# latency=2) hi-z t0 t1 t2 dont care activate command bank b t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank b rbx rbx rax bx0 bx1 ax0 precharge command bank b clk rby cbx cax rby cby bx2 bx3 bx4 bx5 bx6 bx7 ax1 activate command bank a read command bank a activate command bank b read command bank b cs# cke we# a10 ax6 ax7 high rax ax2 ax3 ax4 ax5 t rcd t ac t rp a0-a9, a11-a12 dqm dq ba0,1 ras# cas# AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 35/55 - rev.1.0 june 2016
figure 29 . 2 . random row read (interleaving banks) (burst le ngth=8, cas# latency=3) hi-z t0 t1 t2 dont care activate command bank b t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank b rbx rbx rax bx0 bx1 ax0 precharge command bank b rby cbx cax rby cby bx2 bx3 bx4 bx5 bx6 bx7 ax1 activate command bank a read command bank a activate command bank b read command bank b ax6 ax7 high rax ax2 ax3 ax4 ax5 t rcd t ac t rp precharge command bank a by0 clk cs# cke we# a10 a0-a9, a11-a12 dqm dq ba0,1 ras# cas# AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 36/55 - rev.1.0 june 2016
figure 3 0 . random row write (interleaving banks) (burst length=8) hi-z t0 t1 t2 dont care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 write command bank a rax rax rbx dax3 dax4 dbx3 precharge command bank a ray cax cbx ray cay dax5 dax6 dax7 dbx0 dbx1 dbx2 dbx4 activate command bank b write command bank b activate command bank a write command bank a day1 day2 high rbx dbx5 dbx6 dbx7 day0 t rcd t rp precharge command bank b day3 t wr* t wr* dax0 dax1 dax2 *t wr >t wr (min.) clk cs# cke we# a10 a0-a9, a11-a12 dqm dq ba0,1 ras# cas# AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 37/55 - rev.1.0 june 2016
figure 3 1 . 1 . read and write cycle (burst length=4, cas# latency=2) hi-z t0 t1 t2 dont care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a rax rax day1 cax caz ax0 ax1 ax2 ax3 day0 write command bank a the write data is masked with a zero clock latency read command bank a the read data is masked with a two clock latency az1 az3 cay day3 az0 clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11-a12 dqm dq AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 38/55 - rev.1.0 june 2016
figure 3 1 . 2 . read and write cycle (burst length=4, cas# latency=3) hi-z t0 t1 t2 dont care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a rax rax day1 clk cax caz ax0 ax1 ax2 ax3 day0 write command bank a the write data is masked with a zero clock latency read command bank a the read data is masked with a two clock latency cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11-a12 dqm dq az1 az3 cay day3 az0 AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 39/55 - rev.1.0 june 2016
figure 3 2 . 1 . interleaving column read cycle (burst length=4, cas# latency=2) hi-z t0 t1 t2 dont care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a rax rax rbx ax0 ax1 by0 read command bank a rbx cay cbw ax2 ax3 bw0 bw1 bx0 bx1 by1 activate command bank b read command bank b read command bank b precharge command bank b bz2 bz3 cbx cby cay cbz t rcd t ac read command bank b read command bank b bz0 ay0 ay1 bz1 precharge command bank a clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11-a12 dqm dq AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 40/55 - rev.1.0 june 2016
figure 3 2 . 2 . interleaved column read cycle (burst length=4, cas# latency=3) hi-z t0 t1 t2 dont care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a rax rax rbx ax0 ax1 bz0 precharge command bank b rbx cax cbx ax2 ax3 bx0 bx1 by0 by1 bz1 activate command bank b read command bank b precharge command bank a cby cbz cay t rcd t ac read command bank b read command bank a ay2 ay0 ay1 ay3 read command bank b clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11-a12 dqm dq AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 41/55 - rev.1.0 june 2016
figure 3 3 . interleaved column write cycle (burst length=4) hi-z t0 t1 t2 dont care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 write command bank a rax rax rbw dax0 dax1 dby0 write command bank b clk rbw cax cbw dax2 dax3 dbw0 dbw1 dbx0 dbx1 dby1 activate command bank b write command bank b precharge command bank a cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11-a12 dqm dq cbx cby cay t rcd write command bank b write command bank a dbz0 day0 day1 dbz1 write command bank b cbz t rrd >t rrd (min) t wr t wr dbz2 dbz3 precharge command bank b AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 42/55 - rev.1.0 june 2016
figure 3 4 . 1 . auto precharge after read burst (burst length=4, cas# latency=2) hi-z t0 t1 t2 dont care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a rax rax cbx ax0 ax1 bx0 read with auto precharge command bank a raz cax cay rby cby ax2 ax3 bx1 activate command bank b read with auto precharge command bank b activate command bank b activate command bank a ay2 ay3 high rbx bx2 bx3 ay0 ay1 t rp rby rbx raz by2 by0 by1 read with auto precharge command bank b begin auto precharge bank b begin auto precharge bank a clk cs# cke we# a10 a0-a9, a11-a12 dqm dq ba0,1 ras# cas# AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 43/55 - rev.1.0 june 2016
figure 3 4 . 2 . auto precharge after read burst (burst length=4, cas# latency=3) hi-z t0 t1 t2 dont care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a rax rax rbx bx2 rbx cax cbx ax0 ax1 ax2 ax3 bx0 bx1 bx3 activate command bank b read with auto precharge command bank a read with auto precharge command bank b cay activate command bank b ay2 ay0 ay1 ay3 read with auto precharge command bank b rby t rp begin auto precharge bank b begin auto precharge bank a rby cby by2 by0 by1 high clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11-a12 dqm dq AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 44/55 - rev.1.0 june 2016
figure 3 5 . auto precharge after write burst (burst length=4) hi-z t0 t1 t2 dont care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 write command bank a rax rax rbx dbx2 rbx cax cbx dax0 dax1 dax2 dax3 dbx0 dbx1 dbx3 activate command bank b write with auto precharge command bank a write with auto precharge command bank b cay activate command bank b day2 day0 day1 day3 write with auto precharge command bank b rby t dal begin auto precharge bank b begin auto precharge bank a rby cby dby2 dby0 dby1 high dby3 clk cs# cke we# ba0,1 a10 dqm dq ras# cas# a0-a9, a11-a12 AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 45/55 - rev.1.0 june 2016
figure 3 6 . 1 . full page read cycle (burst length=full page, cas# latency=2) hi-z t0 t1 t2 dont care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a rax rax ax+1 rbx cax rbx ax ax+1 ax+2 ax-2 ax-1 ax bx activate command bank b read command bank b precharge command bank b cbx burst stop command bx+3 bx+1 bx+2 bx+4 the burst counter wraps from the highest order page address back to zero during this time interval t rp rby rby bx+5 bx+6 high full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address activate command bank b clk cs# cke we# a10 dq ras# cas# ba0,1 a0-a9, a11-a12 dqm AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 46/55 - rev.1.0 june 2016
figure 3 6 . 2 . ful l page read cycle (burst length=full page, cas# latency=3) hi-z t0 t1 t2 dont care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a rax rax ax+1 rbx cax rbx ax ax+1 ax+2 ax-2 ax-1 ax bx activate command bank b read command bank b precharge command bank b cbx burst stop command bx+3 bx+1 bx+2 bx+4 the burst counter wraps from the highest order page address back to zero during this time interval t rp rby rby bx+5 high full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address activate command bank b clk cs# cke we# a10 dq ras# cas# ba0,1 a0-a9, a11-a12 dqm AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 47/55 - rev.1.0 june 2016
figure 3 7 . full page write cycle (burst length=full page) hi-z t0 t1 t2 dont care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 write command bank a rax rax dax+1 rbx cax rbx dax dax+1 dax+2 dax+3 dax-1 dax dbx activate command bank b write command bank b precharge command bank b cbx burst stop command dbx+3 dbx+1 dbx+2 dbx+4 the burst counter wraps from the highest order page address back to zero during this time interval rby rby dbx+5 high full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address activate command bank b data is ignored clk cs# cke we# a10 dq ras# cas# ba0,1 a0-a9, a11-a12 dqm AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 48/55 - rev.1.0 june 2016
figure 3 8 . byte read and write operation (bu rst length=4 , cas# latency= 2 ) t0 t1 t2 dont care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a rax rax cax upper byte is masked write command bank a lower byte is masked cay read command bank a lower byte is masked caz clk cs# cke we# a10 dq8-dq15 high lower byte is masked ras# cas# ba0,1 a0-a9, a11-a12 ldqm udqm ax0 ax1 ax2 day1 day2 az1 az2 dq0-dq7 ax1 ax2 ax3 day0 day3 day1 az0 az1 az2 az3 upper byte is masked AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 49/55 - rev.1.0 june 2016
figure 39 . random row read (interleaving banks) (burst length= 4 , cas# latency= 2 ) t0 t1 t2 dont care activate command bank b t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read bank b with auto precharge rbu rbu rau bv0 rau cbu cau bu0 bu1 bu2 bu3 au0 au1 bv1 activate command bank a activate command bank b read bank a with auto precharge rbv activate command bank a av0 bv2 bv3 av1 read bank a with auto precharge cbv t rp begin auto precharge bank a begin auto precharge bank b rav cav high begin auto precharge bank b begin auto precharge bank a rbw rbv rav rbw t rp t rp read bank b with auto precharge au2 au3 av2 av3 activate command bank b clk cs# cke we# a10 dqm dq ras# cas# ba0,1 a0-a9, a11-a12 AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 50/55 - rev.1.0 june 2016
figure 4 0 . full page random column read (burst length=full page, cas# latency=2) hi-z t0 t1 t2 dont care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 activate command bank b rax cax by1 rbx rbx cay ax0 ax1 bx0 ay0 ay1 by0 az0 read command bank a read command bank b precharge command bank b (precharge temination) caz read command bank a bz0 az1 az2 bz1 read command bank a cbz t rp rbw rbw bz2 rax cbx cby t rrd t rcd read command bank b read command bank b activate command bank b clk cs# cke ras# cas# we# a10 dqm dq ba0,1 a0-a9, a11-a12 AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 51/55 - rev.1.0 june 2016
figure 4 1 . full page random column write (burst length=full page) hi-z t0 t1 t2 dont care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 activate command bank b rax cax dby1 rbx rbx cay dax0 dax1 dbx0 day0 day1 dby0 daz0 write command bank a write command bank b precharge command bank b (precharge temination) caz write command bank a dbz0 daz1 daz2 dbz1 write command bank a cbz t rp rbw rbw dbz2 rax cbx cby t rrd t rcd write command bank b write command bank b activate command bank b t wr write data are masked clk cs# cke ras# cas# we# a10 dqm dq ba0,1 a0-a9, a11-a12 AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 52/55 - rev.1.0 june 2016
figure 4 2 . precharge termination of a burst (bur st length=4, 8 or full page, cas# latency=3) t0 t1 t2 dont care activate command bank b t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 rax rax ay0 cax dax0 dax1 ay1 write command bank a activate command bank a activate command bank a ray precharge command bank a ay2 precharge command bank a cay t wr raz high raz ray t rp read command bank a precharge termination of a read burst t rp precharge termination of a write burst write data are masked clk cs# cke we# a10 dqm dq a0-a9, a11-a12 ras# cas# ba0,1 AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 53/55 - rev.1.0 june 2016
figure 4 3 . 54 pin tsop ii package outline drawing information symbol dimension in inch dimension in mm min nom max min nom max a --- --- 0.047 --- - -- 1.2 a1 0.002 --- 0.008 0.05 --- 0.2 a2 0.035 0.039 0.043 0.9 1.0 1.1 b 0.01 0.014 0.018 0.25 0.35 0.45 c 0.004 0.006 0.008 0.12 0.165 0.21 d 0.87 0.875 0.88 22.09 22.22 22.35 e 0.395 0.400 0.405 10.03 10.16 10.29 e --- 0.031 --- --- 0.8 --- he 0 .455 0.463 0.471 11.56 11.76 11.96 l 0.016 0.02 0.024 0.4 0.5 0.6 l1 0.032 --- --- 0.84 --- s --- 0.028 --- --- 0.71 --- y --- --- 0.004 --- --- 0.1 0 --- 8 0 --- 8 AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 54/55 - rev.1.0 june 2016
part numbering system as4c 32m16sb 6/7 t c / i n dram 32m16=32mx16 s = sdram b=b die 6=166 mhz 7=143mhz t = tsopii c=commercial (0 c~+70 c) i = industrial (-40 c~+8 5 c) indicates pb and halogen free alliance memory, inc. 511 taylor way, san carlos, ca 94070 tel: 650-6 10-6800 fax: 650-620-9211 www.alliancememory.com copyright ?alliance memory all rights reserved ?copyright 2007 alliance memory, inc. all rights reserved. our three-point logo, our name and intelliwatt are trademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusively according to alliance's terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components in l ife-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. AS4C32M16SB-6TIN as4c32m16sb-7tin as4c32m16sb-7tcn confidential - 55/55 - rev.1.0 june 2016

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